Switching power converters (SPCs) are widely used in electronic systems to convert a direct current (DC) voltage into a different DC voltage, or an alternating current (AC) voltage into a DC voltage, or a DC voltage into an AC voltage. SPCs are widely used in both portable and non-portable applications for a wide range of power and voltage ranges. There are numerous architectures for each application such as buck (step down), boost (step up), H-bridge, and fly back. Yet, regardless of the type of converter, they all need a controller so that a regulated and well maintained voltage at the output is created. The generated output voltage is often used as a power supply to an specific load within the electronic system. There could be different types of SPCs in one system, each with its own particular load and controller and its particular set of specifications.
FIG. 1 shows block diagram of a typical prior art step-down (or buck) DC/DC switching power converter (SPC) that converts a DC voltage with value of Vin from a power source 11, such as an AC to DC full wave bridge rectifier, into a lowered DC voltage with value of Vout (where Vout<Vin). For example, 12V DC input to power source 11 may be converted to 10V. DC output as Vin. A prior art power converter might convert Vin to a DC output voltage, Vout, of 2 volts DC. The core of a buck SPC is made of two transistor switches; M1 and M2, along with inductor 18A, having a value L0, and capacitor 18B, having a value C0. Transistor M1 can be either a p-channel or a n-channel device, while M2 is customarily a n-channel device. The type selection for M1, between n-channel or p-channel, is heavily dependent on design requirements and availability of devices within the system.
FIG. 2 shows a timing diagram of voltages at nodes 19B, 19C (Vout), 20A and 20B during a steady state condition of the SPC of FIG. 1. By opening and closing transistor switches M1 and M2 in a complementary fashion, at a rate set by a clock oscillator associated with drivers 12 in FIG. 1, where only one device is on at any given moment, the voltage at node 19B would be a pulse with the same frequency of the signal at node 20A or 20B. Yet, the magnitude of the voltage at node 19B would alter from zero to Vin. This pulse voltage would be filtered by inductor 18A and capacitor 18B at node 19C to an approximate value ofVout=Vin(Ton/T)  (1)where Ton is the duration for which M1 is kept conducting (in this case while signal at node 20A is at zero), and T is the total period of signal at node 20A (or period of signal at node 20B). Referring to FIG. 2, the ratio of Ton/T is called “duty cycle” of the clock. So, for a 20 percent “duty cycle”, output voltage Vout would be Vout=0.2Vin assuming no losses.
Returning to FIG. 1, a regulation loop for a prior art SPC is often made of an error amplifier (EA) 23, having an input load Z1, represented by block 14A, and a feedback load Z2, represented by block 14B, a pulse width modulator (PWM) or a pulse frequency modulator (PFM) controller 15, and a driver 12 to turn M1 and M2 on and off. The error amplifier may be an analog or digital device which evaluates a sample of power ripple on one input to the error amplifier versus a reference voltage on node 22C from a reference supply 16. This regulation configuration is frequently seen in buck, boost, and fly-back switching power converter designed of the prior art. An entire SPC system can be built on a printed circuit board using discrete components or it can be built as an integrated circuit using CMOS, BiCMOS, BCD, or any other process technology suitable for such a design.
Referring again to FIG. 2, if value of T is held constant for a constant clock period, or frequency, and Ton (or Toff) is varied to control voltage at node 19C (Vout) then the controller is called a PWM or pulse width modulator controller. Yet, if T is varied and Ton (or Toff) is held constant, then the controller is a PFM or pulse frequency modulator controller. In either case, PWM or PFM, transistor switches M1 and M2 are operated in a manner that creates a voltage pulse at node 19B. Inductor 18A, having a value L0, and capacitor 18B, having a value C0, are connected in a manner to form a low-pass filter so that pulse signal at node 19B is converted into a fairly constant DC voltage at 19C defined by Equation 1 and depicted in FIG. 2. Voltage at node 19C is used to power up any possible load, such as load 13.
Using small-signal analysis, the low-pass filter created by inductor 18A and capacitor 18B produces two poles at fp1, and fp2 that can be calculated from
                              f                      P            ⁢                                                  ⁢            1                          =                              f                          P              ⁢                                                          ⁢              2                                =                      1                          2              ⁢              π              ⁢                                                                    L                    0                                    ⁢                                      C                    0                                                                                                          (        2        )            Now, since there are two poles within the regulation loop, this system would be unstable in a closed loop configuration if there is no change made to the loop. So, the loop must be compensated.
Referring again to FIG. 1, error amplifier 23 along with two loads 14A and 14B, with values Z1 and Z2, respectively, serve as the main compensation circuitry to add stability to the loop. This is a very commonly practiced scheme to compensate a SPC regulator loop. Using small-signal analysis, in the frequency domain, the voltage gain of error amplifier 23 considering its loads can be calculated as
                              A          1                =                                            -              Z                        ⁢                                                  ⁢            2                                Z            ⁢                                                  ⁢            1                                              (        3        )            By using a proper combination of active and passive components, primarily capacitors and resistors for loads Z1 and Z2, proper additional poles and zeros can be added within the regulation loop in order to stabilize it.
FIG. 3 shows one possible method of implementing a complex value for Z2 with a capacitor 101, having a value C11, in series with a resistor 103, having a value R11, both the capacitor 101 and resistor 103 in parallel with capacitor 105, having a value of C12. So. assuming a simple resistor is used for Z1 with value of RZ1, and assuming Z2 is set to be a combination of one resistor and capacitors shown in FIG. 4, then A1 (in Equation 3) is
                              A          1                =                  -                                    1              +                              sRC                11                                                                    R                                  Z                  ⁢                                                                          ⁢                  1                                            ⁢                              s                ⁡                                  [                                                                                    sRC                        11                                            ⁢                                              C                        12                                                              +                                          (                                                                        C                          12                                                +                                                  C                          11                                                                    )                                                        ]                                                                                        (        4        )            with one zero at 1/(2πRC11), and two poles. However, it must be noted that the DC voltage gain of error amplifier 23 is simply equal to its open loop voltage gain, and is not calculated from Equation 4. Furthermore, capacitor 18B, in FIG. 1, having value C0, has series parasitic resistances, not shown in FIG. 1, with a value of Rser which would add another zero at 1/(2πC0Rser). There are effectively two poles created by L0 and C0 (at fP1 and fP2), and two additional poles created by Z1 and Z2 which yield a number of poles totaling four, with two zeros within the loop. Hence, by adjusting the values of passive components L0, C0, (both associated with the bridge converter), C11, C12, R11, (the latter three values seen to be associated with the components of FIG. 3), and RZ1, (the resistance value of the impedance Z1 in block 14A of FIG. 1) a regulation loop can be compensated to ensure a stable operation for all conditions.
The same analysis can be used for any other converter such a fly back, or H-bridge which uses this common type of regulation. One of the main problems in a regulation loop is the error amplifier itself. The error amplifier must have a high voltage gain, and adequate bandwidth in order to be effective. If the voltage gain or speed of the error amplifier is compromised for any reason, then additional error terms are introduced, which in turn may not produce a stable controller. So, performance of the error amplifier is a very crucial and important issue that must be considered for any regulator.
A power supply for an amplifier plays a very crucial role in its gain and bandwidth. A reduced power supply voltage often lowers either the gain or speed, or both gain and speed. Traditionally, error amplifiers in a regulation loop need a minimum power supply voltage of around 2V to operate properly. Furthermore, in a typical buck SPC the entire regulation loop may be powered by the provided power source, which has a value of Vin. Thus, the minimum voltage for power source or (Vin) is often limited to around 2V for a conventional buck SPC. So, if value of Vin drops below this critical limit of around 2V then error amplifier that is used in the buck SPC regulation loop could have a reduced voltage gain or bandwidth, which could hinder the performance of the entire converter, or may prevent operation of the converter.
In a boost converter, where Vin is increased to a larger value at the output and Vout>Vin, if Vin is less than a critical voltage which is need to run all of the internal circuitry, such as error amplifier or reference circuitry, then the output voltage Vout may not be regulated until its value reaches an specific value high enough that can be used as the power source to the regulator itself. Then, the loop is activated to regulate value of Vout at its targeted value.
Thus, general use of an architecture similar to that shown in FIG. 1 in buck SPCs is limited mainly to system where Vin is, at a minimum, around 2V.
Nevertheless, there are applications where a buck SPC is needed to convert a lower voltage power source, such as household batteries that are used as a main power source. In this case Vin could be as low as 1.3V. A desired output voltage (Vout) could be anything from 1.2V to as low as 0.4V.
In such systems, one available scheme could be simply to use a linear voltage regulator. However, efficiency linear voltage regulators is approximated byη=Vout/Vin  (5)where Vin and Vout are their respective input an output voltages. Thus, linear regulator are considered very inefficient for large voltage drops and may not be suitable for a system where Vin=1.3V and Vout=0.65V, since η=50%. An SPC efficiency should be as high as 95% for similar voltage drop ratios. Another available method could be to employ a boost SPC to increase the provided power source by stepping up a value of Vin as previously mentioned to voltage of around 2V, or higher, and then use a buck SPC to regulate the created 2V level back to a voltage lower than the initial Vin. Such an approach would need two sets of SPCs which increases the cost and would reduce the entire efficiency of power converter circuitry. This may not be acceptable, yet it could be the only effective “efficient” solution.
Other approaches to regulate a SPC involve using a digital architecture. In some digital schemes a PLL has been used to monitor and adjust a power supply for a digital system. The goal was to “dynamically” adjust Vout in order to optimize the power consumption of the load which were a large digital circuits. Hence, these approaches are not used to keep Vout at a constant value, but to change it according to the need of an specific digital load in order to minimize the amount of power consumed within such load, such as a micro-controller or microprocessor circuits. An analog-to-digital converter (ADC) has been used to sample the output voltage of a circuit and voltage regulation was done through digital circuitries. However, the input voltage was still kept to a value around 3V to keep an analog-to-digital converter operational. The cost of the die was fairly large.
An object of the invention is to create a new control loop to regulate the output voltage of a switching power converters (SPC), even at low input power supply voltage, particularly lower than 2V, to reduce design complexity, and to lower power consumption and facilitate design portability of the regulator between different manufacturing methods and processes (i.e. CMOS, BiCMOS and such).